We are now looking for a Senior CPU System Software and Infrastructure Architect:
NVIDIA’s invention of the GPU 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as “the AI computing company”. We are looking to grow our teams with the smartest people in the world. If you're creative, autonomous and want to help us continue to reshape computing, we want to hear from you!
What you’ll be doing:
- You will work as part of NVIDIA's CPU architecture team to design and implement hardware and software improvements for future NVIDIA processors.
- Using your experience and knowledge, you will analyze processor workloads using off-the-shelf and custom tools.
- You will architect and implement build, test and profiling infrastructure to drive team productivity
- You will engage with the team in continuing to improve the class leading performance and efficiency of our systems
What we need to see:
- B.S. Degree in CS or ECE or related with 8+ years of relevant experience
- Strong knowledge of computer architecture fundamentals and compiler internals
- Your work should display a real passion for performance optimization and low-level programming
- You have experience working in and programming fluency with C/C++ and assembly languages
- You have designed complex test and build systems with combinations of LSF, grid, perforce, along with other resource management tools
- Strong communication skills are required along with the ability to work in a dynamic product oriented team. An ability and desire to mentor others is a significant advantage.
Ways to stand out from the crowd:
- MS or PhD
- Prior work on a dynamically optimizing system
- Familiarity with details of the ARM architecture
- Experience working with fine-grained or instruction level parallelism